1. Field of the Invention
The present invention relates to a power amplifier for amplifying an input power to produce an output power using transistors. More particularly, the invention relates to a power amplifier comprising cascade-connected amplifier stages that realizes distortion decrease and efficiency increase with respect to signals in the Ultra High Frequency (UHF) band (e.g., 300 to 3000 MHz) to the microwave band (e.g., 1 to 1000 GHz) or millimeter wave band (e.g., 30 to 300 GHz).
2. Description of the Related Art
Recently, mobile or cellular phones have been becoming popular in the mobile communication field and thus, the need for power amplifiers as one of their key devices has been increasing rapidly. Transmitting power amplifiers designed for digital cellular phones need to have characteristics that satisfy high output power, high amplification efficiency, and low distortion. Transmitting power amplifiers are usually formed by high-frequency, high-output bipolar transistors or high-frequency, high-output Metal-Semiconductor Field-Effect Transistors (MESFETs).
Generally, high-frequency, high-output transistors have the following input-output characteristics:
Specifically, the output signal of a high-frequency, high-output transistor increases linearly according to the increase of the input signal when the input signal is low in level. In this case, the range of the linear input-output characteristic is termed the xe2x80x9clinear regionxe2x80x9d. In other words, the transistor is operating in the xe2x80x9clinear regionxe2x80x9d, where distortion is kept in low level.
On the other hand, when the input signal is sufficiently high in level, the output signal of a high-frequency, high-output transistor does not increase linearly according to the increase of the input signal and as a result, the increasing rate of the output signal decreases or saturates. In this case, the range of the input-output characteristic is termed the xe2x80x9csaturation regionxe2x80x9d. The increasing rate decrease of the output signal is termed the xe2x80x9cgain compressionxe2x80x9d. In tho saturation region, the distortion contained in the output signal of a high-frequency, high-output transistor increases.
Therefore, when a multistage power amplifier is configured with high-frequency, high-output transistors to decrease the output signal distortion, conventionally, the operating point of each of the high-frequency, high-output transistors is located at a position on the load line that is back off the saturation region by several decibels (dB). This means that each transistor is operated in a region as close to the linear region as possible, thereby suppressing the distortion in amplification behavior.
With the above-described conventional multistage power amplifier of this type, the back-off amount of each transistor is increased up to a specific level to decrease the distortion in the output signal and therefore, each transistor needs to have a saturation output power enough for maintaining the linearity at the maximum transmission power. This leads to a disadvantage that each transistor needs to have a considerably large size, which raises the cost of the amplifier as well.
Moreover, the obtainable power addition efficiency at an operating point of each transistor backed off the saturation region is less than that at an operating point where the saturation output power is derived. Therefore, there is another problem that each transistor (and therefore, the power amplifier) consumes extra power; i.e., the power efficiency of the amplifier decreases.
The Japanese Non-Examined Patent Publication No. 7-245529 published in 1995 discloses low phase-distortion power amplifiers. A first one of the amplifiers disclosed comprises an amplifier stage with a common-gate Field-Effect Transistor (FET) and an opposite-phase generator stage with a common-source FET. The common-source FET in the opposite-phase generator stage provides a phase change opposite to that of the common-gate FET in the amplifier stage, thereby canceling the phase distortion of the power amplifier. The amplifier stage with the common-gate FET is located prior or next to the opposite-phase generator stage with the common-source FET.
A second one of the amplifier circuits disclosed by the Publication No. 7-245529 comprises an amplifier stage with a common-source FET and an opposite-phase generator stage with a common-gate FET. The common-gate FET in the opposite-phase generator stage provides a phase change opposite to that of the common-source FET in he amplifier stage, thereby canceling the phase distortion of the power amplifier. The amplifier stage with the common-source FET is located prior or next to the opposite-phase generator stage with the common-gate FET.
With the prior-art power amplifiers disclosed by the Publication No. 7-245529, the opposite-phase generator stage compensates or cancels only the xe2x80x9cphase distortionxe2x80x9d. Thus, the technique disclosed by the Publication No. 7-245529 is unable to suppress or prevent the distortion induced by the gain deviation or fluctuation in the amplifier stage.
Accordingly, an object of the present invention is to provide a high-frequency power amplifier having cascade-connected amplifier stages that realizes simultaneously low distortion and high efficiency even when the input or output signal power is near its peak.
Another object of the present invention is to provide a high-frequency power amplifier having cascade-connected amplifier stages that suppresses effectively the distortion induced by gain deviation or fluctuation occurring in at least one of the amplifier stages without using the back-off of the operating point.
Still another object of the present invention is to provide a high-frequency power amplifier having cascade-connected amplifier stages that increases the power addition efficiency while suppressing the distortion.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A high-frequency power amplifier according to the invention comprises:
(a) first to n-th amplifier stages connected in cascade, where n is an integer greater than unity;
(b) a k-th one of the amplifier stages receiving a k-th input signal power to produce a k-th output signal power, where k is an integer satisfying a relationship of 1xe2x89xa6kxe2x89xa6n;
the k-th amplifier stage including a transistor with an amplification function;
the transistor having a gain change in a range of the k-th input signal power or the k-th output signal power;
(c) a m-th one of the amplifier stages receiving a m-th output signal to produce a m-th output signal, where m is an integer satisfying a relationship of 1xe2x89xa6mxe2x89xa6n and mxe2x89xa0k;
the m-th amplifier stage including a transistor with an amplification function;
the transistor having a gain change in a range of the m-th input signal power or the m-th output signal power; and
(d) the gain change of the transistor of the m-th amplifier stage being decreased or cancelled by the gain change of the transistor of the k-th amplifier stage.
With the high-frequency power amplifier according to the invention, the transistor of the k-th amplifier stage has a gain change in a range of the k-th input signal power or the k-th output signal power. The transistor of the m-th amplifier stage has a gain change in a range of the m-th input signal power or the mth output signal power. The gain change of the transistor of the m-th amplifier stage is decreased or cancelled by the gain change of the transistor of the k-th amplifier stage
Therefore, the distortion induced by gain deviation or fluctuation occurring in at lease one of the first to n-th amplifier stages is suppressed effectively without using the back-off. This means that low distortion and high efficiency can be realized simultaneously even when the input or output signal power is near its peak.
Since the back-off is unnecessary, a conventional high-efficiency transistor (which has a gain compression near the peak of its input or output signal power) can be used for the transistor of the k-th or m-th amplifier stage. Thus, the power addition efficiency (and therefore, the output signal power) is increased while suppressing the distortion.
In a preferred embodiment of the amplifier according to the invention, the transistor of the k-th amplifier stage has a gain increase in the range of the k-th input signal power or the k-th output signal power while the transistor of the m-th amplifier stage has a gain compression.
In this embodiment, it is preferred that each of the transistors of the k-th and m-th amplifier stages is a bipolar transistor with common-emitter configuration. Also, the gain change of the transistor of the k-th amplifier stage is preferably caused by changing its base bias current.
Alternately, each of the transistors of the k-th and m-th amplifier stages may be a FET with common-source configuration. The gain change of the transistor of the k-th amplifier stage is preferably caused by changing its gate bias voltage.
In another preferred embodiment of the amplifier according to the invention, a gain controller is additionally provided for controlling a gain of the transistor of the k-th amplifier stage responsive to the k-th output signal power or a n-th output signal power produced by the n-th amplifier stage.
In this embodiment, it is preferred that the transistor of the k-th amplifier stage is a bipolar transistor with common-emitter configuration. Preferably, the gain controller controls a base bias current of the transistor of the k-th amplifier stage.
In still another preferred embodiment of the amplifier according to the invention, relationships of m=k+1 and 1xe2x89xa6kxe2x89xa6(nxe2x88x921) are satisfied.